Instruction-set architecture (ISA) simulators are tools that run on a host machine to mimic the behavior of running an application program on a target machine. Instruction-set simulators are valuable tools in the development of new programmable architectures. They are used to validate architecture and compiler designs, as well as to evaluate architectural design decisions during design space exploration. FIG. 1 depicts a traditional interpretive-simulation technique 10 that is flexible but slow. In interpretive simulation technique 10, an instruction 11 stored in program memory 12 is fetched at 13, decoded at 14, and executed at 15 during run time 16. Since instruction decoding is a time consuming process, the use of interpretive simulation technique 10 can significantly slow the ISA simulation.
FIG. 2 depicts a conventional compiled simulation technique 18 that performs compile time decoding of an application program 20 to improve the simulation performance. Specifically, the application program 20 is compiled in a simulation compiler 21 to create a decoded program 22. That decoded program 22 is passed through a code generation process 23 to create a host assembly 24 stored in program memory 12, which is then executed at 15 by the host 25.
To improve the simulation speed further, static compilation-based techniques, such as compilation technique 18, move the instruction scheduling into the compilation time. However, compiled simulators rely on the assumption that the complete program code is known before the simulation starts and, further more, that the program code is static during run-time. As a result, many application domains are excluded from the utilization of compiled simulators. For example, embedded systems that use external program memories cannot use compiled simulators since the program code is not predictable prior to run-time. Similarly, compiled simulators are not applicable in embedded systems that use processors having multiple instruction sets. These processors can switch to a different instruction set mode at run-time. For instance, the ARM processor uses the Thumb (reduced bit-width) instruction set to reduce power and memory consumption. This dynamic switching of instruction set modes cannot be considered by a simulation compiler 21, since the selection depends on run-time values and is not predictable. Furthermore, applications with run-time dynamic program code, as provided by operating systems (OS), cannot be addressed by compiled simulators.
In recent years, performance of the ISA simulator has steadily grown into one of the most important quality measures for a simulation technique. Also, retargetability has become an important concern, particularly in the area of embedded systems and system-on-chip (SoC) designs. A retargetable ISA simulator would require a generic model, supported by a language, to describe the architecture and its instruction set. The simulator would use the architecture description to decode instructions of the input program and execute them.
However, the creation of a generic model that is efficient in terms of both quality of the architecture description and simulator performance is difficult. To have a high quality description, the model must easily capture the architectural information in a natural, compact and manageable form for a wide range of architectures. Conversely, in order to generate a high performance simulator the model should provide as much static information as possible about the architecture and its instruction set prior to run-time.
Designing an efficient model that captures a wide range of architectures is difficult because each architecture typically has different instruction-set format complexities. Thus, there is a considerable tradeoff between speed and retargetability in ISA simulators. Some retargetable simulators use a very general processor model and support a wide range of architectures but are slow, while others use some architectural or domain specific performance improvements but support only a limited range of processors. Also, in some description languages, deriving a fast simulator requires lengthy descriptions of all possible formats of instructions.
Accordingly, there is a need for improved ISA simulators and simulation methods that address the above concerns and provide advantages over conventional systems and methods.